1. Field of the Invention
The present invention generally relates to a semiconductor layout structure. In particular, the present invention is directed to a semiconductor layout structure with two sets of shallow trench isolations which are neither parallel with nor perpendicular to each other, in order to substantially increase the area of the active area.
2. Description of the Prior Art
In the semiconductor layout structure, an active region accommodates the gate, the source and the drain, which is the core region in a semiconductor element. Besides, because the gate, the source and the drain respectively need a contact plug to electrically connect other circuits upwardly penetrating the interlayer dielectric layer, the size of the contact area of the source, the drain and the gate would directly affect the process window of following etching processes to establish the contact plugs aligning with the gate, the source and the drain, as well as affect the contact resistance of the contact plugs. However, there is no semiconductor layout structure to solve such problems in the current field.
So a novel semiconductor layout structure is still needed to increase the area of the active region in working order, to substantially increase the area of the gate, the source and the drain, to facilitate to increase the etching process window, as well as to effectively reduce the contact resistance of the contact plugs.